Circuit Simulation and DFY

Circuit Design and Process Interface

Semiconductor Process Development

Giga-scale SPICE Simulator – NanoSpice Giga™

Introduction

NanoSpice Giga™ is the industry's first and only GigaSpice, designed for accurate verification and signoff of advanced memory designs, an area where FastSPICE is meeting fundamental limitations. With its innovative parallel simulation engine built on a big data architecture, NanoSpice Giga can handle billion-elements designs, targeting the verification and signoff of various memory circuits, custom or semi-custom digital and full-chip designs. Compared to FastSPICE, NanoSpice Giga uses a pure SPICE engine to offer much higher accuracy for power, leakage, timing and noise characterizations and verifications, Its superior parallelization technologies delivers faster simulation speed without scarifying accuracy. NanoSpice Giga directly replaces FastSPICE and serves as a golden signoff simulator for memory IP and full chip verifications.

Key Benefits

Superior accuracy: true SPICE accuracy with DC convergence, for accurate power/leakage/timing/noise
Giga-scale capacity: handles real full chip verification and signoff (>109 elements)
High performance: faster than FastSPICE and scalable to 32+ threads. Specially optimized for FinFET/FD-SOI models
No FastSPICE options: no tuning, removes guesswork from FastSPICE
Foundry validated accuracy: 16/14/10nm FinFET and 28nm FD-SOI ready

Applications

Embedded memory IP verification
Full chip memory IC verification (DRAM,SRAM,Flash)
Memory characterization
Custom or semi-custom digital: clock tree, critical path analysis

Design Flow Integration

Drop-in replacement of FastSPICE for accurate power/leakage/timing/noise verification and signoff
Plug and run without FastSPICE options and tuning

Model Support

Supports all public domain models, user-defined models and Verilog-A
BSIM3, BSIM4, BSIM6, BSIMSOI, BSIM-CMG, BSIM-IMG, UTSOI, PSP, HSIM2, HiSIM_HV, MOS9, MOS11
Gummel-Poon, VBIC, HICUM, Mextram
Diode, JFET, MESFET, RLC, TFT, TSMC model interface (TMI)

Specifications

Supports Hspice and Spectre netlist formats
Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc
Full SPICE analysis features: OP, DC, AC, Noise, Tran, Info, Sweep, Alter, Monte Carlo, PVT, Tran Noise, PSS, PNOISE, etc
Supports Verilog-A and behavioral sources
Supports VEC and VCD stimulus files
Supports SPEF back-annotation
Supports IBIS model, S-parameter and transmission line, etc

Platform Supported

Redhat Enterprise V4, 5
CentOS V4, 5, 6

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